Senior/Leader Design Verification Engineer

• Verification Planning: Develop and implement verification plans aligned with SoC specifications.
• Testbench Development: Design scalable, reusable testbenches using SystemVerilog and UVM.
• Debugging and Analysis: Identify and resolve design and verification issues.
• Coverage and Quality Assurance: Drive functional and code coverage to meet project goals.
• Leadership: Mentor junior engineers and lead verification for IP blocks or subsystems.
• Automation: Utilize scripting languages (Python, Perl, Tcl) to enhance verification efficiency.

• Bachelor’s or Master’s degree in Electrical Engineering or Electronic Engineering.
• Proven experience in SoC design verification, including unit and combine test strategies. 
• Strong knowledge of AMBA protocols: AHB, APB, AXI (mandatory) and IPs
• Proficiency in verification methodologies such as SystemVerilog, UVM (preferred), and SVA. 
• Familiarity with programming languages like Verilog, assembly, C/C++.
• Proven ability to communicate clearly and transparently with both internal teams and global customers. 
• Capable of managing daily workflows and leading a design team with full ownership and accountability.

Nice to have:

• Basic understanding of formal verification techniques and scripting using TCL, Python.